Conference paper

A Low-Power Programmable Dynamic Frequency Divider

In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.


    • EPFL-CONF-149518

    Record created on 2010-06-24, modified on 2017-05-12


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