A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems
A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three decades. Implemented in 0.13 $\mu$m CMOS, the circuit occupies 0.06 mm$^2$, while its power dissipation is 9 pW/Hz, proportional to the output clock frequency with 350 nW stand-by power. The circuit remains stable with scalable dynamics for frequency steps (upward and downward) as large as a factor of $\times$1024. The presented clock generator is been designed compatible with subthreshold source-coupled logic (STSCL) topology that can be used for ultra-low power applications such as in biomedical systems.
Record created on 2010-06-10, modified on 2016-08-08