A low-power CMOS super-regenerative receiver at 1 GHz
A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes an low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuitry with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm2. The power consumption is less than 1.2 mW at VDD = 1.5 V. A 100-KHz saw tooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency.
Keywords: 0.35 micron;1 GHz;1.5 V;100 kHz;AGC circuit;baseband amplifier;die surface;envelope detector;low-noise amplifier;low-power CMOS;power consumption;sample/hold function;sawtooth quench signal;super-regenerative receiver;CMOS analogue integrated circuits;UHF integrated circuits;field effect MMIC;low-power electronics;microwave receivers;sample and hold circuits;
Record created on 2010-05-21, modified on 2016-08-08