A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes an low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuitry with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm2. The power consumption is less than 1.2 mW at VDD = 1.5 V. A 100-KHz saw tooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency.


Published in:
Solid-State Circuits, IEEE Journal of, 36, 3, 440 -451
Year:
2001
ISSN:
0018-9200
Keywords:
Other identifiers:
Scopus: 2-s2.0-0035273830
Laboratories:




 Record created 2010-05-21, last modified 2018-03-17


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