000145909 001__ 145909
000145909 005__ 20190316234717.0
000145909 037__ $$aPOST_TALK
000145909 245__ $$aRepeater Insertion Techniques for 3D Interconnects
000145909 269__ $$a2010
000145909 260__ $$c2010
000145909 336__ $$aPosters
000145909 520__ $$aA new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.
000145909 6531_ $$a3-D ICs
000145909 6531_ $$arepeater insertion
000145909 6531_ $$aon-chip interconnect
000145909 6531_ $$atiming optimization
000145909 700__ $$aXu, H.
000145909 700__ $$aPavlidis, V.
000145909 700__ $$g167918$$aDe Micheli, G.$$0240269
000145909 7112_ $$dMarch 8-12$$cDresden$$aDATE 2010
000145909 8564_ $$uhttps://infoscience.epfl.ch/record/145909/files/Repeater%20Insertion_.pdf$$zn/a$$s257503
000145909 909C0 $$xU11140$$0252283$$pLSI1
000145909 909CO $$pposter$$qGLOBAL_SET$$ooai:infoscience.tind.io:145909$$pSTI$$pIC
000145909 917Z8 $$x176271
000145909 937__ $$aEPFL-POSTER-145909
000145909 973__ $$sPUBLISHED$$aEPFL
000145909 980__ $$aPOSTER