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A very low power mixed-signal design methodology based on subthreshold source-coupled circuits is presented, and a nano-Watt range analog-to-digital converter (ADC) circuit based on folding-interpolating topology is proposed as a complete design example. To reduce the power dissipation to sub-µW level, subthreshold source-coupled circuit family has been developed for both analog and digital parts. As all the devices are biased in subthreshold, the sampling frequency and power consumption of the ADC can be adjusted over a very wide range. Using pipelined subthreshold source-coupled logic (STSCL) circuits renders the power dissipation of the digital part scalable, and at the same time negligible with respect to the analog part. Implemented in 0.18µm CMOS technology, the active area of the circuit is 0.6mm2. Measured integral nonlinearity (INL), and differential nonlinearity (DNL) of the ADC are 1.0 and 0.4 LSB, respectively, while sampling frequency can be adjusted from 500S/s (17nW) to 80kS/s (1.9μW).