Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.


Presented at:
Nano-Net 2009, Lucern, Switzerland, October 18-20, 2009
Year:
2009
Keywords:
Laboratories:




 Record created 2010-01-15, last modified 2018-03-17

n/a:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)