Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic
An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.
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Keywords: field effect logic circuits ; field effect transistors ; semiconductor device models ; MOSFET models ; SGFET logic circuits ; analytical model ; circuit steady-state behavior ; depletion approximation ; logic circuits ; low-power logic ; mechanical hysteresis ; pull-in voltage ; pull-out voltage ; structural parameters ; suspended-gate FET ; suspended-gate field-effect transistor ; ultra-low power switch ; Electrostatic actuators ; MOSFET ; inverter ; microelectromechanical system (MEMS) ; nanoelectromechanical field-effect transistor (NEMFET) ; nanoelectromechanical systems (NEMS) ; resonant-gate FET ; subthreshold swing ; suspended-gate FET (SGFET)
Record created on 2010-01-08, modified on 2016-08-08