Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied [Omega]- and tri-gate structures to obtain abrupt switching (3-10 mV/decade) combined with a hysteresis in the ID(VDS) and ID(VGS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125 °C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the Ioff. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.


Published in:
Solid-State Electronics, 52, 9, 1336-1344
Year:
2008
ISSN:
0038-1101
Keywords:
Note:
internal-pdf://Punch-through impact ionization MOSFET (PIMOS) From device principle to applica-2478143232/Punch-through impact ionization MOSFET (PIMOS) From device principle to applications.PDF
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 Record created 2010-01-08, last modified 2018-03-18


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