000141935 001__ 141935
000141935 005__ 20180913055518.0
000141935 037__ $$aCONF
000141935 245__ $$aFabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays
000141935 269__ $$a2009
000141935 260__ $$c2009
000141935 336__ $$aConference Papers
000141935 520__ $$aWe describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior.
000141935 6531_ $$ananowire
000141935 6531_ $$aFET
000141935 6531_ $$amultichannel
000141935 6531_ $$aambipolar
000141935 6531_ $$avertical integration
000141935 700__ $$0242417$$aSacchetto, Davide$$g181895
000141935 700__ $$0240267$$aJamaa, Ben$$g169539
000141935 700__ $$aHaykel, M.
000141935 700__ $$0240162$$aDe Micheli, Giovanni$$g112194
000141935 700__ $$0240162$$aLeblebici, Yusuf$$g112194
000141935 7112_ $$a39th European Solid-State Device Research Conference (ESSDERC)$$cAthens, Greece$$dSeptember 14-18, 2009
000141935 773__ $$tProceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
000141935 8564_ $$s1831822$$uhttps://infoscience.epfl.ch/record/141935/files/05331516.pdf$$yn/a$$zn/a
000141935 909C0 $$0252051$$pLSM$$xU10325
000141935 909C0 $$0252283$$pLSI1$$xU11140
000141935 909CO $$ooai:infoscience.tind.io:141935$$pconf$$pSTI$$pIC
000141935 917Z8 $$x112194
000141935 917Z8 $$x112915
000141935 937__ $$aEPFL-CONF-141935
000141935 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000141935 980__ $$aCONF