Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays

We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior.


Published in:
Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
Presented at:
39th European Solid-State Device Research Conference (ESSDERC), Athens, Greece, September 14-18, 2009
Year:
2009
Keywords:
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 Record created 2009-10-15, last modified 2018-09-13

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