Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

In this work a double-gate pentacene TFT architecture is presented. The devices are fabricated on a polyimide substrate using three aligned levels of stencil lithography along with standard photolithography, which enable a soft yet well controlled device processing. The benefic impact of the top gate voltage control to reduce the leakage current and significantly improve the subthreshold swing of the device is demonstrated. Moreover, this original design show good promise for the enhancement of Ion/Ioff TEF characteristics.


Published in:
Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC), 205-208
Presented at:
39th European Solid-State Device Research Conference (ESSDERC), Athens, Greece, September 14-18, 2009
Year:
2009
Publisher:
Athens, IEEE
Keywords:
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2009-09-22, last modified 2018-03-18

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