Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9T memory cell has been developed to reduce the stand-by (leakage) current to 10pA/cell while the SRAM array is operating at 2.1MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer CMOS technology nodes.


Published in:
Proceedings of the European Solid-State Circuits Conference (ESSCIRC), 164-167
Presented at:
European Solid-State Circuits Conference (ESSCIRC), Athens, Greece, September 14-18
Year:
2009
Publisher:
Athens, Greece
Keywords:
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 Record created 2009-07-31, last modified 2018-03-17

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