Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems
The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9T memory cell has been developed to reduce the stand-by (leakage) current to 10pA/cell while the SRAM array is operating at 2.1MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer CMOS technology nodes.
- URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=5325939&isnumber=5325915&punumber=5307451&k2dockey=5325939@ieeecnfs&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=11&access=no
Keywords: Integrated circuits ; CMOS integrated circuits ; Subthreshold source-coupled logic (STSCL) ; Memory ; Static random access memory (SRAM) ; Ultra-low-power ; Integrated circuits ; Leakage current ; Stand-by current
Record created on 2009-07-31, modified on 2016-08-08