Conference paper

1T Memory Cell Based on PVDF-TrFE Field Effect Transistor

Interest in PVDF-TrFE copolymers as ferroelectric material for Memory application is driven by the prospect of having low cost, low operating voltage and fully organic device. Some previous studies reported FET designs using copolymers [refs 1,2] but none of these structures were fully integrated on silicon wafers and using a MOSFET fabrication process. We present for the first time the integration of a PVDF-TrFE (70%-30%) layer into a standard n-MOS transistor through a quasi-standard semiconductor technology. This allows us to achieve a Non Volatile Memory cell and at the same time to compact capacitor-transistor ferroelectric cell into a one-transistor memory cell. The ferroelectric polymer is prepared using a new recipe based on Methyl-Ethyl-Ketone, which helps to reduce considerably the film thickness and the coercive field. The solution is deposited by spin coating down to 100nm and the structures are defined by standard UV lithography. We add a 10nm SiO2 layer between the polymer and the p-doped substrate in order to reduce losses and the screening in the ferroelectric gate (Fig.1a). The ferroelectric properties of the polymer are preserved during the whole process (Fig.1b). We design, fabricate and characterize transistors of different dimensions (from 50μm down to 2μm as channel length and width) demonstrating a good scalability. Experimental Id(Vg) and Id(Vd) curves for different channel lengths and widths are in agreement with the theoretical predictions for such a device (Id (W/L)Vd. Fig.2-3). The device shows very good hysteresis properties translated in a controllable and reproducible memory behavior. The change in current, due to the polarization of the ferroelectric layer, is in the order of 10^5 and the off-state current is about 10^-9A (Fig. 2-3). Moreover we are able to program the device at about 10V with a programming time in the order of μs. Ageing tests by accumulating multiple cycling have also been performed. We cycled the Vg potential and measured the Drain/Source current after successive series of cycles on same device. After 10^5 cycles the change in the on-state current is about 10% while the one for the off-state current is about 25% but the current window is large enough that the two states are clearly distinguishable. For the retention measurements we apply a voltage pulse on the gate and measure the time response of the drain and source currents. It is found that the retention time depends on the FET dimensions. This can be as long as 3 days for the large transistors (L=W=50μm) and about 5 to 3 hours for smaller ones (for L=W=10μm and L=W=2μm, respectively). This demonstrates the usability of these devices for any disposable electronic applications requiring memory storage for few days.


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