Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO₂ gate stack
This work experimentally demonstrates, for the first time, that by integrating a thin ferroelectric layer into a gate stack of a standard MOS transistor one, it is possible to overcome the 60 mV/decade subthreshold swing limit at room temperature of MOSFET. We find sub-threshold swings as low as 13 mV/decade in Fe-FETs with 40 nm P(VDF-TrFE)/SiO₂ gate stack. The mechanism governing the low subthreshold swing in Fe-FET transistors is the negative capacitance of the ferroelectric layer that provides voltage amplification; with our particular ferroelectric gate stack we report for the first time negative capacitance at room temperature.
Keywords: MOSFET ; ferroelectric thin films ; silicon compounds ; Fe-FET ; P(VDF-TrFE)/SiO2 gate stack ; SiO2 ; negative capacitance ; size 40 nm ; standard MOS transistor ; subthrehold swing ; thin ferroelectric layer ; voltage amplification
Record created on 2009-07-15, modified on 2016-08-08