The recently proposed PIMOS transistor can offer, by appropriate operation, non-hysteretic abrupt off-on transitions due to impact ionization if the action of its parasitic bipolar transistor is minimized. This work proposes non-hysteretic abrupt inverter circuits based on <10 mV/decade room temperature current switching and a tunable negative differential resistance based on punch-through impact ionization MOS transistors (PIMOS) when parasitic bipolar action is cancelled by choosing an appropriate drain voltage. The proposed circuit architectures are compatible with silicon CMOS nodes. The very abrupt non-hysteretic inverter shows gain of the order of -100 in the transition region of the voltage transfer characteristic (VTC). The NDR circuit exhibits tunable peak-to-valley PVR values and a negative resistance in the range of hundreds of kOmega.