Compact Modeling of Suspended Gate FET

For the first time, a compact model for suspended gate (SG) FET valid for entire bias range is proposed. The model is capable of simulating both pull-in and pull-out effects, which are the two important phenomena of this device. A novel hybrid numerical simulation approach combining ANSYS Multiphysics and ISE-DESSIS in a self-consistent system is developed. The model is then validated on this numerical device simulation of SGFET. The model shows excellent performance over the entire drain and gate voltage range. The model has been implemented in Verilog-A code and tested on ELDO and Spectre simulators, which makes it useful for circuit simulations using SGFET devices.


Published in:
VLSI Design, 2008. VLSID 2008. 21st International Conference on, 119-124
Year:
2008
ISSN:
1063-9667
Keywords:
Laboratories:




 Record created 2009-07-15, last modified 2018-09-13


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