A UML Based System Level Failure Rate Assessment Technique for SoC Designs

This paper proposes an analytical method to assess softerror rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method uses an executable UML model of the SoC for its input. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. SER and execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.


Published in:
Proceedings of the 25th IEEE VLSI Test Symmposium, 243-248
Presented at:
25th IEEE VLSI Test Symposium, Berkeley, May 6-10, 2007
Year:
2007
Publisher:
Berkeley
Laboratories:




 Record created 2009-05-23, last modified 2018-09-13


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