Stall Power Reduction in Pipelined Architecture Processors

This paper proposes a technique for dynamic power reduction of pipelined processors. Pipelined processors frequently insert NOP instruction to the pipe for generating delay or resolving dependency. Our study shows that the percentage of power consumed by NOP instructions in a pipelined processor is significant. This article studies the detail behavior of NOP instruction and proposes a technique for eliminating unnecessary transitions that are generated during execution of NOP instructions. Initial results demonstrate up to 10% reduction in power consumption for some benchmarks at a cost of negligible performance (almost zero) and area overhead (below 0.1%).


Published in:
Proceedings of the 21st International Conference on VLSI Design, 541-546
Presented at:
21st International Conference on VLSI Design, Hyderabad, January 4-8, 2008
Year:
2008
Publisher:
Hyderabad
Laboratories:




 Record created 2009-05-23, last modified 2018-03-17


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