Low test application time resource binding for behavioral synthesis

Recent advances in process technology have led to a rapid increase in the density of integrated circuits (ICs). Increased density and the need to test for new types of defects in nanometer technologies have resulted in a tremendous increase in test application time (TAT). This article presents a test synthesis method to reduce test application time for testing the datapath of a design. The test application time is reduced by applying a test-time-aware resource sharing algorithm on a scheduled control data flow graph (CDFG) of a design.


Published in:
ACM Transactions on Design Automation of Electronic Systems, 12, 2, 16
Year:
2007
Keywords:
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 Record created 2009-05-23, last modified 2018-09-13


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