A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the testability of individual RTL operations within the RTL circuit. Using a non-scan arrangement, existing data paths are utilised to provide controllability and observability to RTL operations. Furthermore, additional data paths are introduced by altering the controller states or adding new transitions. This method considerably reduces the test application time by ignoring unnecessary control states in the test process. The proposed method is applied to behavioural and RTL benchmarks. The results show the effectiveness of this method when compared with some other DFT insertion methods.