Gated-Vdd: a circuit technique to reduce leakage in deep- submicron cache memories

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V<sub>dd</sub>, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V<sub>dd</sub> together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance

Published in:
Proceedings of the International Symposium on Low Power Electronics and Design, 90-95
Presented at:
International Symposium on Low Power Electronics and Design (ISLPED), Rapallo, Italy, July

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 Record created 2009-04-06, last modified 2019-12-05

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