000135561 001__ 135561
000135561 005__ 20180317093434.0
000135561 0247_ $$2doi$$a10.1109/ISCA.2000.854385
000135561 037__ $$aCONF
000135561 245__ $$aSelective, accurate, and timely self-invalidation using last-touch prediction
000135561 260__ $$c2000
000135561 269__ $$a2000
000135561 336__ $$aConference Papers
000135561 520__ $$aCommunication in cache-coherent distributed shared memory (DSM) often  requires invalidating (or writing back) cached copies of a memory block,  incurring high overheads. This paper proposes Last-Touch Predictors (LTPs)  that learn and predict the “last touch” to a memory block by one processor  before the block is accessed and subsequently invalidated by another. By  predicting a last-touch and (self-)invalidating the block in advance, an LTP  hides the invalidation time, significantly reducing the coherence overhead.  The key behind accurate last-touch prediction is trace-based correlation,  associating a last-touch with the sequence of instructions (i.e. a trace)  touching the block from a coherence miss until the block is invalidated.  Correlating instructions enables an LTP to identify a last-touch to a memory  block uniquely throughout an application's execution. In this paper we use  results from running shared-memory applications on a simulated DSM to  evaluate LTPs. The results indicate that: (1) our base case LTP design  maintaining trace signatures on a per-block basis, substantially improves  prediction accuracy over previous self-invalidation schemes to an average of  79%; (2) our alternative LTP design, maintaining a global trace signature  table, reduces storage overhead but only achieves an average accuracy of  58%; (3) last-touch prediction based on a single instruction only achieves an  average accuracy of 41% due to instruction reuse within and across  computation; and (4) LTP enables selective, accurate, and timely self- invalidation in DSM, speeding up program execution on average by 11%
000135561 700__ $$aLai, An-Chow
000135561 700__ $$0243553$$aFalsafi, Babak$$g177958
000135561 7112_ $$cVancouver, BC$$dJune
000135561 773__ $$q139 - 148$$tProceedings of the International Symposium on Computer Architecture
000135561 8564_ $$zURL
000135561 8564_ $$s143624$$uhttps://infoscience.epfl.ch/record/135561/files/isca00.pdf$$zn/a
000135561 909CO $$ooai:infoscience.tind.io:135561$$pIC$$pconf
000135561 909C0 $$0252231$$pPARSA$$xU11837
000135561 937__ $$aPARSA-CONF-2000-001
000135561 970__ $$a6651738/PARSA
000135561 973__ $$aOTHER$$rREVIEWED$$sPUBLISHED
000135561 980__ $$aCONF