000133584 001__ 133584
000133584 005__ 20190415234806.0
000133584 020__ $$a978-0-387-74908-2
000133584 037__ $$aBOOK_CHAP
000133584 245__ $$aDesigning Routing and Message-Dependent Deadlock Free Networks on Chips
000133584 269__ $$a2008
000133584 260__ $$bSpringer$$c2008$$aLondon
000133584 336__ $$aBook Chapters
000133584 490__ $$aIFIP Advances in Information and Communication Technology$$v249
000133584 520__ $$aNetworks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks that can occur in NoCs can be broadly categorized into two classes: routing-dependent deadlocks and message-dependent deadlocks. In this work, we present methods to design NoCs that avoid both types of deadlocks. The methods are integrated with the topology synthesis phase of the NoC design flow. We show that by considering the deadlock avoidance issue during topology synthesis, we can obtain a significantly better NoC design than traditional methods, where the deadlock avoidance issue is dealt with separately. Our experiments on several SoC benchmarks show that our proposed scheme provides large reduction in NoC power consumption (an average of 38.5%) and NoC area (an average of 30.7%) when compared to traditional approaches.
000133584 6531_ $$aNetwork-on-Chip
000133584 6531_ $$aSystem-on-Chip
000133584 6531_ $$aPower consumption
000133584 6531_ $$aArea
000133584 6531_ $$aDeadlocks
000133584 6531_ $$aDesign method
000133584 700__ $$0240269$$g167918$$aDe Micheli, Giovanni
000133584 700__ $$aMir, Salvador
000133584 700__ $$aReis, Ricardo
000133584 700__ $$0242414$$g171633$$aMurali, Srinivasan
000133584 700__ $$aMeloni, Paolo
000133584 700__ $$0241996$$g169841$$aAngiolini, Federico
000133584 700__ $$0240268$$g169199$$aAtienza, David
000133584 700__ $$aCarta, Salvatore
000133584 700__ $$aBenini, Luca$$g171049$$0243773
000133584 700__ $$aRaffo, Luigi
000133584 773__ $$j1$$tVLSI-SoC: Research Trends in VLSI and Systems on Chip$$q337-356
000133584 8564_ $$uhttp://www.springer.com/computer/communication+networks/book/978-0-387-74908-2$$zURL
000133584 8564_ $$uhttps://infoscience.epfl.ch/record/133584/files/bookchapter.pdf$$zn/a$$s371335$$yn/a
000133584 909C0 $$xU11140$$0252283$$pLSI1
000133584 909C0 $$0252050$$pESL$$xU11977
000133584 909CO $$pSTI$$pbook$$pIC$$pchapter$$ooai:infoscience.tind.io:133584$$qGLOBAL_SET
000133584 917Z8 $$x112915
000133584 917Z8 $$x112915
000133584 937__ $$aEPFL-CHAPTER-133584
000133584 973__ $$sPUBLISHED$$aEPFL
000133584 980__ $$aCHAPTER