Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs
Ayala, Jose L.; Atienza, David; Lopez-Vallejo, Marisa; Mendias, Jose M.; Hermida, Roman
2005

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Abstract

In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties.

Details

Title Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs
Author(s) Ayala, Jose L. ; Atienza, David ; Lopez-Vallejo, Marisa ; Mendias, Jose M. ; Hermida, Roman
Published in Proceedings of the III IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘05)
Pages 65-71
Conference III IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘05), Oahu, Hawaii, USA, January 19-21, 2005
Date 2005
Publisher New York, IEEE Press
ISSN 1527-1366
Keywords
DOI https://doi.org/10.1109/IWIA.2005.35
Laboratories ESL
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > ESL - Embedded Systems Laboratory
Peer-reviewed publications
Work outside EPFL
Conference Papers
Published
Record creation date 2009-01-11

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