Compilation for Delay Impact Minimization in VLIW Embedded Systems

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new compilation approach to mitigate the performance implications of technology variation in the shared register file in upcoming embedded VLIW architectures with several processing units. The compilation approach is based on a redefined register assignment policy and a set of architectural modifications to this device. Experimental results show up to a 67% performance improvement with our technique.


Published in:
Proceedings of the IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘06), 1, 1, 83-90
Presented at:
IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘06), Kona, Hawaii, USA, January 21-23, 2006
Year:
2006
Publisher:
New York, IEEE Press
Keywords:
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 Record created 2009-01-11, last modified 2018-09-13

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