Systematic Intermediate Sequence Removal for Reduced Memory Accesses

Modern software applications are growing in complexity and demand very intensive use of data. Therefore, a wide variety of data structures are utilized to facilitate the storage and access to these vast amounts of computed information. Additionally, the need for reliable software design and the development of large applications following the object-oriented paradigm increase the amount of dynamic buffers and redundant accesses to the data stored in these buffers. In this paper, we propose a systematic, design optimization methodology to remove these intermediate dynamic buffers, thereby reducing the memory accesses of the targeted applications without altering the input-output behaviour of the algorithms. The reduction is focused on sequences and is especially relevant for embedded systems, which have limited on-chip communication bandwidth and the energy consumption of the memory subsystem is high, due to the energy consumption associated with each memory access. The effectiveness of the proposed methodology is assessed in a 3D reconstruction multimedia application and shows a significant reduction in memory accesses. In addition, the general trends for memory improvement and the scalability of our approach are supported as well by a parameterized benchmark set.


Published in:
Proceedings of the 10th ACM International Workshop on Software & Compilers for Embedded Systems (SCOPES), 235, 1, 51-60
Presented at:
10th ACM International Workshop on Software & Compilers for Embedded Systems (SCOPES), Nice, France, April 23-24, 2007
Year:
2007
Publisher:
Amsterdam, ACM
Keywords:
Laboratories:




 Record created 2009-01-11, last modified 2018-03-17

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