A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs. In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field- Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications.


Published in:
321-326
Presented at:
16th IFIP/IEEE International Conference on Very Large Scale Integration, Rhodes, Greece, October 13-15, 2008
Year:
2008
Laboratories:




 Record created 2008-12-24, last modified 2018-09-13

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