Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis
The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today’s grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT)manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logictoGDSII traversing the conventional CMOS design flow; thereby staging an accurate comparison between CMOS and CNFETbased circuits. Our experimental results show that for an optimal choice, with respect to EnergyDelay Product (EDP), CNFET based inverter can achieve 4.2x gain in delay, 2x gain in energy/cycle and 1.4x gain in area when compared to corresponding CMOS inverter benchmarked with an industrial 65nm technology.