000129421 001__ 129421
000129421 005__ 20190316234425.0
000129421 0247_ $$2doi$$a10.1109/JSSC.2008.2010788
000129421 02470 $$2ISI$$a000263032100020
000129421 037__ $$aARTICLE
000129421 245__ $$aA Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology
000129421 269__ $$a2009
000129421 260__ $$c2009
000129421 336__ $$aJournal Articles
000129421 520__ $$aThis article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation in low supply voltages using a conventional 0.18um CMOS technology feasible. The output driver circuit consumes 4.5mA while driving an external 100-Ohm resistor with an output voltage swing of VOD = 400mV, achieving a normalized power dissipation of 3.42mW/Gbps. The area of the LVDS driver circuit is 0.067mm2 and the measured output jitter is sigma_{rms} = 4.5ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5Gbps where the speed will be limited by the load RC time constant.
000129421 6531_ $$aCMOS integrated circuits
000129421 6531_ $$aCurrent-mode logic (CML)
000129421 6531_ $$aLow-voltage differential signaling (LVDS)
000129421 6531_ $$aOutput driver
000129421 6531_ $$aSource-coupled logic (SCL)
000129421 700__ $$0242440$$aTajalli, Armin$$g167171
000129421 700__ $$0240162$$aLeblebici, Yusuf$$g112194
000129421 773__ $$j44$$k2$$q538-548$$tIEEE Journal of Solid-State Circuits
000129421 8564_ $$uhttp://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4768867&isnumber=4768865&punumber=4&k2dockey=4768867@ieeejrns&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=2&access=no$$zURL
000129421 8564_ $$s1201255$$uhttps://infoscience.epfl.ch/record/129421/files/09_JSSC_LVDS_Tajalli.pdf$$zn/a
000129421 909C0 $$0252051$$pLSM$$xU10325
000129421 909CO $$ooai:infoscience.tind.io:129421$$pSTI$$particle$$qGLOBAL_SET
000129421 937__ $$aLSM-ARTICLE-2008-018
000129421 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000129421 980__ $$aARTICLE