Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

This article presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. A source follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18um CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing high performance subthreshold SCL (STSCL) library cells with more efficiency in terms of power consumption and Si area. An optimized approach for designing library cells is proposed to improve the power efficiency.

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IEEE Transaction on Circuits and Systems-II, 56, 2, 127-131

 Record created 2008-11-20, last modified 2018-01-28

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