On the Reliability of Post-CMOS and SET Systems

The necessity of applying fault-tolerant techniques to increase the reliability of future nano-electronic systems is an undisputed fact, dictated by the high density of faults that will plague these chips. The averaging and thresholding fault-tolerant technique that has proven remarkable efficiency in CMOS is presented for SET-based designs. Computer simulations demonstrate the superiority of this fault-tolerant technique over other methods, which is specifically the case when an adaptable threshold is used.


Published in:
International Journal of Nanotechnology and Molecular Computation (IJNMC), 1
Year:
2009
Keywords:
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Note: The status of this file is: EPFL only


 Record created 2008-10-29, last modified 2018-03-17

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