Quick and Clean: Stencil Lithography for Wafer-Scale Fabrication of Superconducting Tunnel Junctions

This paper presents a resist-less process for parallel fabrication of sub-micrometer Al-AlOx-Al superconducting tunnel junctions. A custom stencil is fabricated containing 200 nm low-stress SiN membranes with micro-apertures. The stencil is aligned and clamped with a 1 mu m accuracy to a substrate wafer containing Ti-Au contact electrodes. The junctions are fabricated by evaporating Al from two different angles, with an intermediate in-situ oxidation step. Measurements of the devices down to 0.3 K show stencil lithography is a good candidate for parallel, resist-less patterning of sub-micrometer area tunnel junctions. Challenges are addressed and further developments are proposed.


Presented at:
Applied Superconductivity Conference 2008 (ASC 2008), Chicago, Illinois USA, August 17-22 2008
Year:
2008
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Note: The status of this file is: EPFL only


 Record created 2008-09-04, last modified 2018-03-17

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