Non volatile flash memories based on nanoparticles (nps) are one of the identified routes to a further downscaling of future CMOS technology. New features such as Coulomb blockade and quantized charging effects can appear at room temperature only for a limited number of addressed nanometer sized nps [1]. It has been previously demonstrated that ultra low energy ion implantation (1keV) into an ultra thin SiO2 layer (7nm) through a stencil mask containing apertures (from 50nm to 2μm) [2], followed by annealing allows to produce 2D arrays of Si nps into localized areas of the gate oxide [3]. The I(t) and I(V) measurements of the nano-MOS capacitors reveal single electron transport at room temperature. At the same time, the C(V) electrical measurements reveal significant flat-band voltage shift as high as 4V denoting strong memory effect in these isolated areas. However, as a result of ion implantation damage into the oxide, the remaining structural defects (e.g. excess of silicon atoms, Si/SiO2 interface defects…) and their localization play a major part in the electrical characteristics of these devices. In this paper, we propose a complementary electrical study using AFM/Kelvin Probe (KFM) technique. The amount of charges stored in each nps with different sizes can be evaluated from the surface potential change with the electron injection into and extraction from the ncs. Moreover, the temporal decay of the surface potential has been systematically studied as a function of ncs characteristics (density, size, localization…) and the retention time extracted from the exponential decay was found much longer than 4000s in the implanted areas. These measurements clearly add to the understanding of memories based on these nanostructures.