Pico-Watt Source-Coupled Logic Circuits

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18um CMOS technology, the bias current of each STSCL gate can be reduced below 10pA, which corresponds to a power-delay product (PDP) of less than 500aJ.


Published in:
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Presented at:
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Rhodes Island, Greece, October 13-15
Year:
2008
Publisher:
Greece
Keywords:
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 Record created 2008-08-05, last modified 2018-09-13

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