Improving the power-delay performance in subthreshold source-coupled logic circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated.


Editor(s):
Svensson, Lars
Monteiro, Jose
Published in:
Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 21-30
Presented at:
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 10-12
Year:
2008
Publisher:
Portugal, Springer
Keywords:
Laboratories:




 Record created 2008-07-10, last modified 2018-09-13

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