000124989 001__ 124989
000124989 005__ 20190316234305.0
000124989 0247_ $$2doi$$a10.5075/epfl-thesis-4162
000124989 02470 $$2urn$$aurn:nbn:ch:bel-epfl-thesis4162-0
000124989 02471 $$2nebis$$a5586769
000124989 037__ $$aTHESIS
000124989 041__ $$aeng
000124989 088__ $$a4162
000124989 245__ $$aCross connected multilevel voltage source inverter topologies for medium voltage applications
000124989 269__ $$a2008
000124989 260__ $$aLausanne$$bEPFL$$c2008
000124989 300__ $$a256
000124989 336__ $$aTheses
000124989 520__ $$aMultilevel voltage source inverters where first introduced in the early 1980s. Since then, they have been continuously developed, offering a wide new research area in power electronics. The popularity of multilevel solutions come from the advantages that they offer: improved output quality, voltage sharing in high voltage applications, increased power density or reduction of filtering costs. Two completely new and innovative cross-connected topological families for advanced multilevel voltage source inverters are introduced in this thesis. The motivation for this work stems out from the need to generate multiple output levels while keeping the reliability as high as possible. The offered solutions are able to address the problematic, but of course they do not come without a price: A higher control complexity and more semiconductor blocking voltage capability are necessary in the design of such advanced converters. The Cross Connected Intermediate Level (CCIL) Voltage Source Inverter is the first of the two new topologies presented here. It is built as a cascade of stages using capacitors which are connected to each other by means of cross connected cell structures. The CCIL can be used in several configurations, like redundant or non-redundant switching state configurations for instance. A graphical model based on the physical properties of the inverter is proposed and an original fuzzy logic controller is designed for the balancing of the capacitor voltages and modulation of the inverter. The control algorithm is implemented and verified in simulations. The results are used to benchmark the topology against standard solutions and the conclusions are used to define what applications could benefit from such a converter structure. The Common Cross Connected Stage (CCCS) Voltage Source Inverter is the second original contribution of this work in terms of topology. It is built using the cross connected stage and its capacitor in a common configuration for the three phases of the inverter. Such a design allows to use only one stage per three phases. Because of the intrinsic three phased properties of this topology, a model based on space phasor representation is introduced. With the help of this model, a novel space phasor modulation strategy is derived and proposed. It allows to generate the three phased output voltages while using the available redundancies for balancing of the capacitor voltages. The resulting algorithm is first implemented and tested in simulation, and in a second step a test setup is built and the modulator is coded in VHDL. The simulation and experimental results obtained validate the topology and control concepts. A benchmarking of the CCCS solution is also done to understand what are the benefits and drawbacks of this solution. Analysis and comparison of the new topologies allow to evaluate in an objective way the contributions brought by this work. It is found that the newly proposed solutions cover an area of multilevel inverters where not so many solutions were available prior to this work: Generation of multiple output levels with reduced number of passive and active components (thus increasing the reliability). The drawback is a higher blocking voltage requirement. Conclusions and case study are proposed to help assess the expected performances and choose the most suitable solutions for given applications.
000124989 586__ $$aABB, 2009
000124989 6531_ $$aDC-AC voltage source inverter
000124989 6531_ $$amultilevel converter
000124989 6531_ $$across connected
000124989 6531_ $$aphase capacitors
000124989 6531_ $$amedium voltage
000124989 6531_ $$aharmonic distortion
000124989 6531_ $$apower density
000124989 6531_ $$atopology
000124989 6531_ $$aconvertisseur de tension DC-AC
000124989 6531_ $$aonduleur multiniveaux
000124989 6531_ $$across connected
000124989 6531_ $$acapacités de phase
000124989 6531_ $$amoyenne tension
000124989 6531_ $$adistortion harmonique
000124989 6531_ $$adensité de puissance
000124989 6531_ $$atopologie
000124989 700__ $$aChaudhuri, Toufann
000124989 720_2 $$0241026$$aRufer, Alfred$$edir.$$g106311
000124989 8564_ $$uhttp://vpaa.epfl.ch/Jahia/site/vpaa/op/edit/lang/fr/pid/34588$$zAward
000124989 8564_ $$s12466183$$uhttps://infoscience.epfl.ch/record/124989/files/EPFL_TH4162.pdf$$yTexte intégral / Full text$$zTexte intégral / Full text
000124989 909C0 $$0252144$$pLEI$$xU10314
000124989 909CO $$ooai:infoscience.tind.io:124989$$pthesis$$pthesis-bn2018$$pDOI$$pSTI$$qDOI2$$qGLOBAL_SET
000124989 918__ $$aSTI$$cIEL$$dEDEY
000124989 919__ $$aLEI
000124989 920__ $$b2008
000124989 970__ $$a4162/THESES
000124989 973__ $$aEPFL$$sPUBLISHED
000124989 980__ $$aTHESIS