Pentacene - SiO2 interface: role of the environment prior to pentacene deposition and its impact on TFT DC characteristics

In this paper we report on the effect of the environment on the SiO2/pentacene interface. Two batches of bottom-contact pentacene thin-film transistors have been fabricated with a 100 nm thick SiO2 as dielectric. Considerable shifts of the threshold voltages have been observed for the TFTs whose dielectric surface has been exposed to air for long periods of storage before depositing the pentacene layer. Based on reports from other research groups in the field, we consider that long exposure of the SiO2 to air may have the same effect on the SiO2-pentace interface as short but more aggressive oxygen plasma treatment.

Presented at:
26th International Conference on Microelectronics, Nis, Serbia, May 11-14 2008

Note: The status of this file is: EPFL only

 Record created 2008-06-02, last modified 2018-09-13

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