000124944 001__ 124944
000124944 005__ 20190604054636.0
000124944 02470 $$2ISI$$a000257413400069
000124944 037__ $$aARTICLE
000124944 245__ $$aEtching of sub-micrometer structures through Stencil
000124944 269__ $$a2008
000124944 260__ $$c2008
000124944 336__ $$aJournal Articles
000124944 520__ $$aResistless processes to realize the pattern transfer of your designs into the substrate present some advantages, as the reduction in fabrication steps. Stencil Lithography (SL) is one of the most used resistless processes and, up to now, it has mainly been used to perform local selective deposition of materials. Here, the local etching of different substrates through a stencil hard mask is presented. The compatibility with different etching conditions, the scalability of the technique and the main challenges are described. Minimum feature dimensions of 500 nm in polysilicon and 200 nm in LS-SiN is presented.
000124944 700__ $$0240380$$g176631$$aVillanueva, G.
000124944 700__ $$0240328$$g169048$$aVazquez-Mena, O.
000124944 700__ $$0240119$$g152156$$avan den Boogaart, M. A. F.
000124944 700__ $$0240329$$g172982$$aSidler, K.
000124944 700__ $$g165951$$aPataky, K.$$0240330
000124944 700__ $$aSavu, V.$$g176597$$0245968
000124944 700__ $$aBrugger, J.$$g145781$$0240120
000124944 773__ $$j85$$tMicroelectronic Engineering$$q1010-1014
000124944 8564_ $$uhttps://infoscience.epfl.ch/record/124944/files/Villanueva_2008_MicroEng_Etching%20through%20stencil.pdf$$zn/a$$s1431482
000124944 909C0 $$xU12739$$0252546$$pNEMS
000124944 909C0 $$pLMIS1$$xU10321$$0252040
000124944 909CO $$qGLOBAL_SET$$pSTI$$particle$$ooai:infoscience.tind.io:124944
000124944 917Z8 $$x176631
000124944 937__ $$aLMIS1-ARTICLE-2008-034
000124944 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000124944 980__ $$aARTICLE