Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs

The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an FPGA. To exploit the FPCA, a circuit is transformed by merging disparate addition and multiplication operations into large multi-input addition operations, which are synthesized as compressor trees on the FPCA; the remaining portion of the circuit is synthesized on the FPGA. This paper presents a series of architectural improvements to the FPCA that reduce routing delay, increase flexibility and component utilization, and simplify the integration process. Using an FPGA containing six FPCAs, we observed average and maximum speedups of 1.60x and 2.40x on a set of arithmetic benchmarks

Published in:
Proceedings of the 16th international ACM/SIGDA Symposium on Field programmable Gate Arrays, 181-190
Presented at:
FPGA '08: International Symposium on Field Programmable Gate Array, Monterey, CA, USA, February 24-26 February
New York, NY, USA, ACM

 Record created 2008-04-23, last modified 2018-01-28

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