MOS current-mode logic standard cells for high-speed low-noise applications

With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integrated circuit is inevitably transmitted to the analog parts, through the power supply networks and through the common silicon substrate. Therefore, in the past years a lot of attention has been drawn to alternative digital logic circuit styles that are more friendly than classical CMOS in a mixed-signal environment. MOS Current-Mode Logic (MCML) is a differential logic circuit style that provides high-speed operation together with low generation of supply noise, and is thus a natural candidate for implementing digital blocks in mixed-signal circuits. In this work, MOS Current-Mode Logic circuits are studied, with a focus on the implementation of standard-cell based digital circuits. To this aim, a design methodology is proposed to build efficient MCML standard-cell libraries, and a complete top-down design flow allowing the construction of complex digital circuits with differential standard-cells is proposed. The results of implementing a digital encoder block for analog-to-digital applications are presented.

Leblebici, Yusuf
Lausanne, EPFL
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis4098-1

Note: The status of this file is: EPFL only

 Record created 2008-04-18, last modified 2018-03-17

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