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This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate contacts are used as gate- controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in sub-threshold CMOS circuits. Measurements in conventional 0.18um CMOS technology show that the tail bias current of each gate can be set as low as 10pA, with a supply voltage of 300mV. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.