Improving the Power-Delay Product in SCL Circuits Using Source Follower Output Stage

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) in an SCL gate by a factor close to two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultralow power applications. Designed in conventional digital 0.18um CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.


Published in:
Proceedings of the International Symposum on Circuits and Systems (ISCAS), 145 - 148
Presented at:
International Symposum on Circuits and Systems (ISCAS), Seattle, Washington, USA, May 18-21
Year:
2008
Publisher:
Seattle, Washington, USA, IEEE
Keywords:
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 Record created 2008-03-07, last modified 2018-03-17

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