Three-dimensional electronic devices fabricated on a top-down silicon nanowire platform
For the past couple of decades the desire to add more complexity to a computer chip, while simultaneously reducing the cost per bit, has been accommodated by down-scaling. This approach has been extremely successful in the past, but like all good things it will eventually come to an end. Today, transistor dimensions are approaching the physical limits, and device performance is limited by leakage and short-channel effects. Three dimensional devices are considered as a replacement for planar devices due to their superior control of short channel effects. In this work, I have addressed three of the issues facing modern nanoelectronics: improved gate control and mobility enhancement by strain engineering is demonstrated in a bended gate-all-around (GAA) MOSFET; less than 10mV/decade switching transients are shown in an Ω-gate punch-through impact ionization MOSFET (PIMOS); and the issue of interconnect is addressed by an assessment of photonic global interconnect, centered around a GAA electro-optical modulator. The GAA architecture is acknowledged as the ultimate device architecture in terms of control of short-channel effects. In the present work, a new low-cost top-down local SOI fabrication method is presented, which relies on smart processing of bulk silicon to obtain dimensions beyond that of the lithographic resolution. Strain has become a major performance booster in CMOS technologies, because it can increase the mobility, and thereby the current drive, without negatively affecting the other device parameters. In the top-down nanowire fabrication platform presented here, local oxidation-induced bending of the nanowires is demontsrated, which remains after gate stack deposition and isolation. The bending gives rise to tensile strain on the order of 1-3%, and results in a mobility enhancement compared to non-bended devices of around 100%. The subthreshold slope of the MOSFET determines the ability to turn off the device. In devices based on drift-diffusion transport it is limited to 60mV/decade at room temperature. Here, we present a novel device based on impact ionization in the punch-through region of a MOSFET, combined with an Ω-gate structure. The PIMOS shows abrupt on-off and off-on transitions of less than 10mV/decade combined with hysteresis in both the ID(VGS) and ID(VDS). To our best knowledge, the first abrupt hysteretic inverter based on this principle is experimentally demonstrated. To address the issue of delay and power dissipation in global interconnect, photonic interconnect is accepted as a possible solution. Photonic interconnect requires the availability of a light source, optical waveguide, electro-optical modulator and a photo-detector. As a result of their nature one material cannot fulfill all of these. We focus on silicon as the ideal waveguiding medium. Suspended optical waveguides are fabricated in parallel with electronic devices on the top-down silicon nanowire platform and a preliminary characterization is carried out. Furthermore, the performance of a GAA electro-optical modulator is evaluated by 3D electrical and optical simulation. The GAA structure combines the high speed of capacitive operation, with a relatively high modulation efficiency, as a consequence of the good overlap between the modulated region and the optical mode.
Keywords: Silicon nanowire ; Gate-All-Around MOSFET ; Strain ; Mobility enhancement ; Impact ionization ; Optical interconnect ; nanofil ; silicium ; grille enrobante ; MOSFET ; silicium contraint ; mobilité ; ionisation par impact ; interconnexion optiqueThèse École polytechnique fédérale de Lausanne EPFL, n° 4068 (2008)
Programme doctoral Microsystèmes et Microélectronique
Faculté des sciences et techniques de l'ingénieur
Institut de génie électrique et électronique
Laboratoire des dispositifs nanoélectroniques
Record created on 2008-03-06, modified on 2016-08-08