Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. We propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25\u03bcm, 0.18\u03bcm and 0.13\u03bcm CMOS).


Published in:
Proceedings of the IEEE International Symposium on Circuits and Systems, 1871 - 1874
Presented at:
IEEE International Symposium on Circuits and Systems, New Orleans, Louisiana, USA, May 27-30
Year:
2007
Publisher:
None, None
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 Record created 2007-12-13, last modified 2018-01-28

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