Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits
This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance (FTOL) requirements of the system are simultaneously satisfied. A test chip has been implemented in standard digital 0.18 μm CMOS while the proposed CDR circuit consumes only 10.5 mW and occupies 0.045 mm2 silicon area in 2.5 Gbps data bit rate. Measurement results show a good agreement to analyses proofs the capabilities of the proposed approach for implementing low-power GO CDRs.
- URL: http://www.ingentaconnect.com/content/asp/jolpe/2007/00000003/00000003/art00011?token=00431d623e5acbff093b57e442f2067214876342544495b5f7c4038687630505d79
Record created on 2007-12-03, modified on 2016-08-08