A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication
This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 um CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gbps/channel and occupying a silicon area of 0.045 mm2/channel, with the total aggregate data bit rate of 20 Gbps. The measured FTOL is 3.5% and no error was detected for a 231-1 PRBS (pseudo-random bit stream) input data for 30 minutes meaning that the bit error rate (BER) is smaller than 10-12. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning-range and compensated loop-gain has been applied to tune the center frequency of all CDR channels on desired frequency.
- URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?arnumber=4317714&isnumber=4317684&punumber=4&k2dockey=4317714@ieeejrns&query=%28%28tajalli+a.%29%3Cin%3Eau+%29&pos=4&access=no
Keywords: Chip-to-chip interconnection ; Clock and data recovery circuit ; CMOS integrated circuits ; Frequency tolerance ; Gated-oscillator ; Jitter tolerance ; Optical data communication ; Short-haul ; Analog circuits
Record created on 2007-09-18, modified on 2016-08-08