Full wafer integration of NEMS on CMOS by nanostencil lithography

Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nanodevices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively.


Published in:
Electron Devices Meeting, 2006. IEDM '06. International, 1-4
Presented at:
2006 IEEE international Electron Devices, Electron Devices Meeting, Electron Devices Meeting, 2006. IEDM '06. International, December 11-13,, San Francisco, U.S.A., December 11-13, 2006
Year:
2006
Publisher:
San Francisco, U.S.A.
Laboratories:




 Record created 2007-09-14, last modified 2018-03-17

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