Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device

A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is introduced. Measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can be utilized successfully for bias currents as low as 1 nA, achieving sufficiently high gain (>3) over a wide frequency range.


Published in:
IEE Electronics Letters, 43, 17, 911-913
Year:
2007
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 Record created 2007-07-25, last modified 2018-03-17

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