Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores
This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.
Case Study of Fault Tolerant Architectures-final.pdf
restricted
233.33 KB
Adobe PDF
8f8a074bf58c609a32325b0ce7270eea