Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown.


Published in:
17th Edition of the Great Lakes Symposium on VLSI (GLSVLSI), 204 - 207
Presented at:
Great Lakes Symp. on VLSI (GLSVLSI), 2007, Stresa-Lago Maggiore, Italy, March 11-13
Year:
2007
Publisher:
ACM
Keywords:
Laboratories:




 Record created 2007-06-26, last modified 2018-10-01

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